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Enhanced Filter Coprocessor
if underflow occurred) after every MAC operation. The 16-bit result from the FMAC is stored in
the EFCOP output buffer, FDOR.
10.3 EFCOP Operation
DSP56311 EFCOP operation is determined by the control bits in the EFCOP Control/Status
Register (FCSR), described in Section 10.4.5 . Further filtering operations are enabled via the
appropriate bits in the FACR and FDCH registers. After the FCSR is configured to the mode of
choice, enable the EFCOP by setting FCSR[FEN].
Note:
To ensure proper EFCOP operation, most FCSR bits must be changed only while the
EFCOP is enabled.
Table 10-2 summarizes the EFCOP operating modes.
Table 10-2. EFCOP Operating Modes
FCSR Bits
Mode Description
3
6
FMLC
5–4
FOM
3
FUPD 2
2
FADP 2
1
FLT
0
FEN
EFCOP Disabled 1
FIR, Real, single channel
FIR, Real, adaptive, single channel
FIR, Real, coeff. update, single channel
FIR, Real, adaptive + coeff. update,
x
0
0
0
0
x
00
00
00
00
x
0
0
1
1
x
0
1
0
1
x
0
0
0
0
0
1
1
1
1
single channel
FIR, Real, multichannel
FIR, Real, adaptive, multichannel
FIR, Real, coeff. update, multichannel
FIR, Real, adaptive + coeff. update,
1
1
1
1
00
00
00
00
0
0
1
1
0
1
0
1
0
0
0
0
1
1
1
1
multichannel
FIR, Full Complex, single channel
FIR, Complex Alternating, single channel
FIR, Magnitude, single channel
IIR, Real, single channel
IIR, Real, multichannel
0
0
0
0
1
01
10
11
00
00
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
Notes: 1.
2.
3.
10-6
An x indicates that the specified value can be 1 or 0.
If the user sets the FUPD bit, the EFCOP updates the coefficients and clears the FUPD bit. The adaptive mode
(that is, FADP = 1) sets the FUPD bit, which causes the EFCOP to update the coefficients and then
automatically clear the FUPD bit. Therefore, the value assigned to the FUPD bit in this table refers only to its
initial setting and not its dynamic state during operation.
All bit combinations not defined by this table are reserved for future development.
DSP56311 Reference Manual, Rev. 2
Freescale Semiconductor
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